c = rcar_pwrc_get_mpidr_cluster(mpidr);
dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
- if (RCAR_PRODUCT_M3 == product && cut <= RCAR_M3_CUT_VER11)
+ if (RCAR_PRODUCT_M3 == product && cut < RCAR_CUT_VER30)
goto done;
if (RCAR_PRODUCT_H3 == product && cut <= RCAR_CUT_VER20)
product = reg & RCAR_PRODUCT_MASK;
cut = reg & RCAR_CUT_MASK;
- if (product == RCAR_PRODUCT_M3)
+ if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30)
goto self_refresh;
if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
mmio_write_32(DBSC4_REG_DBRFEN, 0U);
rcar_micro_delay(1U);
- if (product == RCAR_PRODUCT_M3)
+ if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30)
return;
if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
/* DBTR16 */
/* WDQL : tphy_wrlat + tphy_wrdata */
tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1);
- /* DQENLTNCY : tphy_wrlat = WL-2 */
+ /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0
+ * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0
+ */
tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1);
/* DQL : tphy_rdlat + trdata_en */
/* it is not important for dbsc */
/* periodic dram zqcal and phy ctrl update enable */
mmio_write_32(DBSC_DBCALCNF, 0x01000010);
if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
- || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) {
+ || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
} else {
#if RCAR_DRAM_SPLIT == 2
}
if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
- || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) {
+ || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
} else {
mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
foreach_vch(ch)
mmio_write_32(DBSC_DBPDLK(ch), 0x00000000);
if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))
- || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20))) {
+ || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) {
/* non : H3 Ver.1.x/M3-W Ver.1.x not support */
} else {
mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
* SPDX-License-Identifier: BSD-3-Clause
*/
-#define BOARDNUM 18
+#define BOARDNUM 19
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
0, 0, 0, 0, 0, 0, 0, 0}
}
}
- }
+ },
+/* boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) */
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x04, 0x04},
+ 0x00543210,
+ 0x3201,
+ {0x70612543, 0x43251670, 0x45326170, 0x10672534},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x04, 0x04},
+ 0x00543210,
+ 0x2310,
+ {0x01327654, 0x34526107, 0x35421670, 0x70615324},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
};
void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
} else if (Prr_Product == PRR_PRODUCT_M3N) {
/* RENESAS SALVATOR-X (M3-N/SIP) */
brd = 11;
- } else if (Prr_Product == PRR_PRODUCT_M3) {
+ } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W/SIP) */
brd = 0;
+ } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) {
+ /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */
+ brd = 18;
}
}
#endif
* SPDX-License-Identifier: BSD-3-Clause
*/
-#define RCAR_DDR_VERSION "rev.0.34"
+#define RCAR_DDR_VERSION "rev.0.35rc01"
#define DRAM_CH_CNT (0x04)
#define SLICE_CNT (0x04)
#define CS_CNT (0x02)
--- /dev/null
+/*
+ * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+#include "qos_init_m3_v30.h"
+
+#define RCAR_QOS_VERSION "rev.0.1"
+
+#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
+#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
+
+#define QOSWT_TIME_BANK0 (20000000U) //unit:ns
+
+#define QOSWT_WTEN_ENABLE (0x1U)
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 (SL_INIT_SSLOTCLK_M3_30 - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT (3U)
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT (9U)
+#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0 (5U)
+#define WT_BASE_SUB_SLOT_NUM0 (12U)
+#define QOSWT_WTSET0_PERIOD0_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U)
+#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
+#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 -1U)
+
+#define QOSWT_WTSET1_PERIOD1_M3_30 ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_M3_30)-1U)
+#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_REQ_SSLOT0 -1U)
+#define QOSWT_WTSET1_SLOTSLOT1 (WT_BASE_SUB_SLOT_NUM0 -1U)
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+
+/* Same as M3 Ver.1.1 default setting */
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3_v11_mstat195.h"
+#else
+#include "qos_init_m3_v11_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+/* Same as M3 Ver.1.1 default setting */
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_m3_v11_qoswt195.h"
+#else
+#include "qos_init_m3_v11_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif
+
+static void dbsc_setting(void)
+{
+ uint32_t md=0;
+
+ /* Register write enable */
+ io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
+
+ /* BUFCAM settings */
+ io_write_32(DBSC_DBCAM0CNF1, 0x00043218); //dbcam0cnf1
+ io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2
+ io_write_32(DBSC_DBCAM0CNF3, 0x00000000); //dbcam0cnf3
+ io_write_32(DBSC_DBSCHCNT0, 0x000F0037); //dbschcnt0
+ io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0
+ io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0
+
+ md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17;
+
+ switch (md) {
+ case 0x0:
+ /* DDR3200 */
+ io_write_32(DBSC_SCFCTST2, 0x012F1123);
+ break;
+ case 0x1: //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4)
+ /* DDR2800 */
+ io_write_32(DBSC_SCFCTST2, 0x012F1123);
+ break;
+ case 0x4: //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4)
+ /* DDR2400 */
+ io_write_32(DBSC_SCFCTST2, 0x012F1123);
+ break;
+ default: //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4)
+ /* DDR1600 */
+ io_write_32(DBSC_SCFCTST2, 0x012F1123);
+ break;
+ }
+
+ /* QoS Settings */
+ io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
+ io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
+ io_write_32(DBSC_DBSCHQOS02, 0x00000000);
+ io_write_32(DBSC_DBSCHQOS03, 0x00000000);
+ io_write_32(DBSC_DBSCHQOS40, 0x00000300);
+ io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
+ io_write_32(DBSC_DBSCHQOS42, 0x00000200);
+ io_write_32(DBSC_DBSCHQOS43, 0x00000100);
+ io_write_32(DBSC_DBSCHQOS90, 0x00000100);
+ io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
+ io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
+ io_write_32(DBSC_DBSCHQOS93, 0x00000040);
+ io_write_32(DBSC_DBSCHQOS120, 0x00000040);
+ io_write_32(DBSC_DBSCHQOS121, 0x00000030);
+ io_write_32(DBSC_DBSCHQOS122, 0x00000020);
+ io_write_32(DBSC_DBSCHQOS123, 0x00000010);
+ io_write_32(DBSC_DBSCHQOS130, 0x00000100);
+ io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
+ io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
+ io_write_32(DBSC_DBSCHQOS133, 0x00000040);
+ io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
+ io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
+ io_write_32(DBSC_DBSCHQOS142, 0x00000080);
+ io_write_32(DBSC_DBSCHQOS143, 0x00000040);
+ io_write_32(DBSC_DBSCHQOS150, 0x00000040);
+ io_write_32(DBSC_DBSCHQOS151, 0x00000030);
+ io_write_32(DBSC_DBSCHQOS152, 0x00000020);
+ io_write_32(DBSC_DBSCHQOS153, 0x00000010);
+
+ /* Register write protect */
+ io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
+}
+
+void qos_init_m3_v30(void)
+{
+ dbsc_setting();
+
+ /* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+ #if RCAR_LSI == RCAR_M3
+ #error "Don't set DRAM Split 4ch(M3)"
+ #else
+ ERROR("DRAM Split 4ch not supported.(M3)");
+ panic();
+ #endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
+ (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+ NOTICE("BL2: DRAM Split is 2ch\n");
+ io_write_32(AXI_ADSPLCR0, 0x00000000U);
+ io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
+ | ADSPLCR0_SPLITSEL(0xFFU)
+ | ADSPLCR0_AREA(0x1DU)
+ | ADSPLCR0_SWP);
+ io_write_32(AXI_ADSPLCR2, 0x00001004U);
+ io_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else
+ NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+ NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+ NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_RAS, 0x00000044U);
+ io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+ io_write_32(QOSCTRL_DANT, 0x0020100AU);
+ io_write_32(QOSCTRL_FSS, 0x0000000AU);
+ io_write_32(QOSCTRL_INSFC, 0x06330001U);
+ io_write_32(QOSCTRL_EARLYR, 0x00000001U);
+ io_write_32(QOSCTRL_RACNT0, 0x02010003U); /* GPU Boost Mode ON */
+
+ /* GPU Boost Mode */
+ io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
+
+ io_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_M3_30);
+ io_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_M3_30 << 16)));
+
+ {
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ io_write_64(QOSBW_FIX_QOS_BANK0 + i*8,
+ mstat_fix[i]);
+ io_write_64(QOSBW_FIX_QOS_BANK1 + i*8,
+ mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ io_write_64(QOSBW_BE_QOS_BANK0 + i*8,
+ mstat_be[i]);
+ io_write_64(QOSBW_BE_QOS_BANK1 + i*8,
+ mstat_be[i]);
+ }
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+ io_write_64(QOSWT_FIX_WTQOS_BANK0 + i*8,
+ qoswt_fix[i]);
+ io_write_64(QOSWT_FIX_WTQOS_BANK1 + i*8,
+ qoswt_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+ io_write_64(QOSWT_BE_WTQOS_BANK0 + i*8,
+ qoswt_be[i]);
+ io_write_64(QOSWT_BE_WTQOS_BANK1 + i*8,
+ qoswt_be[i]);
+ }
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+ }
+
+ /* RT bus Leaf setting */
+ io_write_32(RT_ACT0, 0x00000000U);
+ io_write_32(RT_ACT1, 0x00000000U);
+
+ /* CCI bus Leaf setting */
+ io_write_32(CPU_ACT0, 0x00000003U);
+ io_write_32(CPU_ACT1, 0x00000003U);
+ io_write_32(CPU_ACT2, 0x00000003U);
+ io_write_32(CPU_ACT3, 0x00000003U);
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ /* re-write training setting */
+ io_write_32(QOSWT_WTREF, ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+ io_write_32(QOSWT_WTSET0, ((QOSWT_WTSET0_PERIOD0_M3_30 << 16) | (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+ io_write_32(QOSWT_WTSET1, ((QOSWT_WTSET1_PERIOD1_M3_30 << 16) | (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+ io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ io_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ io_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
--- /dev/null
+/*
+ * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_H_M3_V30__
+#define QOS_INIT_H_M3_V30__
+
+void qos_init_m3_v30(void);
+
+#endif /* QOS_INIT_H_M3_V30__ */
BL2_SOURCES += drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+ BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
else ifdef RCAR_LSI_CUT_COMPAT
ifeq (${RCAR_LSI},${RCAR_H3})
ifeq (${RCAR_LSI},${RCAR_M3})
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+ BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
endif
ifeq (${RCAR_LSI},${RCAR_M3N})
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c
else ifeq (${LSI_CUT},11)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
- else
-# LSI_CUT 11 or later
+ else ifeq (${LSI_CUT},13)
BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
+ else ifeq (${LSI_CUT},30)
+ BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
+ else
+# LSI_CUT 30 or later
+ BL2_SOURCES += drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c
endif
endif
ifeq (${RCAR_LSI},${RCAR_M3N})
/* define used for M3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
#define SUB_SLOT_CYCLE_M3_11 (0x84U) /* 132 */
+#define SUB_SLOT_CYCLE_M3_30 (0x84U) /* 132 */
#else /* REF 3.9usec */
#define SUB_SLOT_CYCLE_M3_11 (0x108U) /* 264 */
+#define SUB_SLOT_CYCLE_M3_30 (0x108U) /* 264 */
#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
#define SL_INIT_SSLOTCLK_M3_11 (SUB_SLOT_CYCLE_M3_11 -1U)
+#define SL_INIT_SSLOTCLK_M3_30 (SUB_SLOT_CYCLE_M3_30 -1U)
#define QOSWT_WTSET0_CYCLE_M3_11 ((SUB_SLOT_CYCLE_M3_11 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
+#define QOSWT_WTSET0_CYCLE_M3_30 ((SUB_SLOT_CYCLE_M3_30 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */
#endif
#define OPERATING_FREQ (400U) /* MHz */
#include "H3/qos_init_h3_v30.h"
#include "M3/qos_init_m3_v10.h"
#include "M3/qos_init_m3_v11.h"
+#include "M3/qos_init_m3_v30.h"
#include "M3N/qos_init_m3n_v10.h"
#endif
#if RCAR_LSI == RCAR_H3 /* H3 */
#if RCAR_LSI == RCAR_M3 /* M3 */
#include "M3/qos_init_m3_v10.h"
#include "M3/qos_init_m3_v11.h"
+#include "M3/qos_init_m3_v30.h"
#endif
#if RCAR_LSI == RCAR_M3N /* M3N */
#include "M3N/qos_init_m3n_v10.h"
#define PRR_PRODUCT_10 (0x00U)
#define PRR_PRODUCT_11 (0x01U)
#define PRR_PRODUCT_20 (0x10U)
+#define PRR_PRODUCT_21 (0x11U)
#define PRR_PRODUCT_30 (0x20U)
#if !(RCAR_LSI == RCAR_E3)
case PRR_PRODUCT_10:
qos_init_m3_v10();
break;
- case PRR_PRODUCT_20: /* M3 Cut 11 */
- default:
+ case PRR_PRODUCT_21: /* M3 Cut 13 */
qos_init_m3_v11();
break;
+ case PRR_PRODUCT_30: /* M3 Cut 30 */
+ default:
+ qos_init_m3_v30();
+ break;
}
#else
PRR_PRODUCT_ERR(reg);
PRR_PRODUCT_ERR(reg);
}
qos_init_m3_v10();
+#elif RCAR_LSI_CUT == RCAR_CUT_11
+ /* M3 Cut 11 */
+ if ((PRR_PRODUCT_M3 | PRR_PRODUCT_20)
+ != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ qos_init_m3_v11();
+#elif RCAR_LSI_CUT == RCAR_CUT_13
+ /* M3 Cut 13 */
+ if ((PRR_PRODUCT_M3 | PRR_PRODUCT_21)
+ != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ qos_init_m3_v11();
#else
- /* M3 Cut 11 or later */
+ /* M3 Cut 30 or later */
if ((PRR_PRODUCT_M3)
!= (reg & (PRR_PRODUCT_MASK))) {
PRR_PRODUCT_ERR(reg);
}
- qos_init_m3_v11();
+ qos_init_m3_v30();
#endif
#elif RCAR_LSI == RCAR_M3N /* M3N */
/* M3N Cut 10 or later */
case PRR_PRODUCT_10:
break;
case PRR_PRODUCT_20: /* M3 Cut 11 */
+ case PRR_PRODUCT_21: /* M3 Cut 13 */
+ case PRR_PRODUCT_30: /* M3 Cut 30 */
default:
refperiod = REFPERIOD_CYCLE;
break;
#if RCAR_LSI_CUT == RCAR_CUT_10
/* M3 Cut 10 */
#else
- /* M3 Cut 11 or later */
+ /* M3 Cut 11 */
+ /* M3 Cut 13 */
+ /* M3 Cut 30 or later */
refperiod = REFPERIOD_CYCLE;
#endif
#elif RCAR_LSI == RCAR_M3N /* for M3N */
product = reg & RCAR_PRODUCT_MASK;
cut = reg & RCAR_CUT_MASK;
- if (product == RCAR_PRODUCT_M3)
+ if (product == RCAR_PRODUCT_M3 && RCAR_CUT_VER30 > cut)
goto tlb;
if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut)
break;
}
- if (RCAR_PRODUCT_M3_CUT11 == product_cut) {
- NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", str);
+ if ((RCAR_PRODUCT_M3 == product) &&
+ (RCAR_CUT_VER20 == (reg & RCAR_MAJOR_MASK))) {
+ if (RCAR_M3_CUT_VER11 == (reg & RCAR_CUT_MASK)) {
+ /* M3 Ver.1.1 or Ver.1.2 */
+ NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n",
+ str);
+ } else {
+ NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n",
+ str,
+ (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET);
+ }
} else {
major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
major = major + RCAR_MAJOR_OFFSET;
#define RCAR_PRODUCT_M3N U(0x00005500)
#define RCAR_PRODUCT_E3 U(0x00005700)
#define RCAR_CUT_VER10 U(0x00000000)
-#define RCAR_CUT_VER11 U(0x00000001) /* H3/M3N Ver.1.1 */
+#define RCAR_CUT_VER11 U(0x00000001) /* H3/M3N/E3 Ver.1.1 */
#define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */
#define RCAR_CUT_VER20 U(0x00000010)
#define RCAR_CUT_VER30 U(0x00000020)
#define RCAR_MAJOR_SHIFT U(4)
#define RCAR_MINOR_SHIFT U(0)
#define RCAR_MAJOR_OFFSET U(1)
+#define RCAR_M3_MINOR_OFFSET U(2)
#define RCAR_PRODUCT_H3_CUT10 (RCAR_PRODUCT_H3 | U(0x00)) /* 1.0 */
#define RCAR_PRODUCT_H3_CUT11 (RCAR_PRODUCT_H3 | U(0x01)) /* 1.1 */
#define RCAR_PRODUCT_H3_CUT20 (RCAR_PRODUCT_H3 | U(0x10)) /* 2.0 */
#include <arch_helpers.h>
-#define VERSION_OF_RENESAS "2.0.0"
+#define VERSION_OF_RENESAS "2.0.1"
#define VERSION_OF_RENESAS_MAXLEN (128)
extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];
$(eval $(call add_define,RCAR_AUTO))
RCAR_CUT_10:=0
RCAR_CUT_11:=1
+RCAR_CUT_13:=3
RCAR_CUT_20:=10
RCAR_CUT_30:=20
$(eval $(call add_define,RCAR_CUT_10))
$(eval $(call add_define,RCAR_CUT_11))
+$(eval $(call add_define,RCAR_CUT_13))
$(eval $(call add_define,RCAR_CUT_20))
$(eval $(call add_define,RCAR_CUT_30))
RCAR_LSI_CUT:=0
else ifeq (${LSI_CUT},11)
RCAR_LSI_CUT:=1
+ else ifeq (${LSI_CUT},13)
+ RCAR_LSI_CUT:=3
+ else ifeq (${LSI_CUT},30)
+ RCAR_LSI_CUT:=20
else
$(error "Error: ${LSI_CUT} is not supported.")
endif
# disable compatible function.
ifeq (${LSI_CUT},10)
RCAR_LSI_CUT:=0
+ else ifeq (${LSI_CUT},11)
+ RCAR_LSI_CUT:=1
else
$(error "Error: ${LSI_CUT} is not supported.")
endif
projects / project / bcm63xx / atf.git / commitdiff